upse-r3000-abstract.h 4.2 KB

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  1. /*
  2. * UPSE: the unix playstation sound emulator.
  3. *
  4. * Filename: upse-r3000-abstract.h
  5. * Purpose: libupse: r3K abstract implementation factory headers
  6. *
  7. * Copyright (c) 2007 William Pitcock <nenolod@sacredspiral.co.uk>
  8. * Portions copyright (c) 1999-2002 Pcsx Team
  9. * Portions copyright (c) 2004 "Xodnizel"
  10. *
  11. * UPSE is free software, released under the GNU General Public License,
  12. * version 2.
  13. *
  14. * A copy of the GNU General Public License, version 2, is included in
  15. * the UPSE source kit as COPYING.
  16. *
  17. * UPSE is offered without any warranty of any kind, explicit or implicit.
  18. */
  19. #ifndef _UPSE__LIBUPSE__UPSE_R3000_ABSTRACT_H__GUARD
  20. #define _UPSE__LIBUPSE__UPSE_R3000_ABSTRACT_H__GUARD
  21. #include <stdio.h>
  22. #include "upse-internal.h"
  23. typedef union
  24. {
  25. struct
  26. {
  27. u32 r0, at, v0, v1, a0, a1, a2, a3, t0, t1, t2, t3, t4, t5, t6, t7, s0, s1, s2, s3, s4, s5, s6, s7, t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
  28. } n upse_packed_t;
  29. u32 r[34]; /* Lo, Hi in r[33] and r[34] */
  30. } psxGPRRegs;
  31. typedef union
  32. {
  33. struct
  34. {
  35. u32 Index, Random, EntryLo0, EntryLo1,
  36. Context, PageMask, Wired, Reserved0,
  37. BadVAddr, Count, EntryHi, Compare,
  38. Status, Cause, EPC, PRid, Config, LLAddr, WatchLO, WatchHI, XContext, Reserved1, Reserved2, Reserved3, Reserved4, Reserved5, ECC, CacheErr, TagLo, TagHi, ErrorEPC, Reserved6;
  39. } n upse_packed_t;
  40. u32 r[32];
  41. } psxCP0Regs;
  42. typedef struct
  43. {
  44. psxGPRRegs GPR; /* General Purpose Registers */
  45. psxCP0Regs CP0; /* Coprocessor0 Registers */
  46. u32 pc; /* Program counter */
  47. u32 code; /* The instruction */
  48. u32 cycle;
  49. u32 interrupt;
  50. } upse_r3000_cpu_registers_t;
  51. extern upse_r3000_cpu_registers_t upse_r3000_cpu_regs;
  52. #define _i32(x) (s32)x
  53. #define _u32(x) (u32)x
  54. #define _i16(x) (s16)x
  55. #define _u16(x) (u32)x
  56. #define _i8(x) (s8)x
  57. #define _u8(x) (u8)x
  58. /**** R3000A Instruction Macros ****/
  59. #define _PC_ upse_r3000_cpu_regs.pc // The next PC to be executed
  60. #define _Funct_ ((upse_r3000_cpu_regs.code ) & 0x3F) // The funct part of the instruction register
  61. #define _Rd_ ((upse_r3000_cpu_regs.code >> 11) & 0x1F) // The rd part of the instruction register
  62. #define _Rt_ ((upse_r3000_cpu_regs.code >> 16) & 0x1F) // The rt part of the instruction register
  63. #define _Rs_ ((upse_r3000_cpu_regs.code >> 21) & 0x1F) // The rs part of the instruction register
  64. #define _Sa_ ((upse_r3000_cpu_regs.code >> 6) & 0x1F) // The sa part of the instruction register
  65. #define _Im_ ((u16)upse_r3000_cpu_regs.code) // The immediate part of the instruction register
  66. #define _Target_ (upse_r3000_cpu_regs.code & 0x03ffffff) // The target part of the instruction register
  67. #define _Imm_ ((s16)upse_r3000_cpu_regs.code) // sign-extended immediate
  68. #define _ImmU_ (upse_r3000_cpu_regs.code&0xffff) // zero-extended immediate
  69. #define _rRs_ upse_r3000_cpu_regs.GPR.r[_Rs_] // Rs register
  70. #define _rRt_ upse_r3000_cpu_regs.GPR.r[_Rt_] // Rt register
  71. #define _rRd_ upse_r3000_cpu_regs.GPR.r[_Rd_] // Rd register
  72. #define _rSa_ upse_r3000_cpu_regs.GPR.r[_Sa_] // Sa register
  73. #define _rFs_ upse_r3000_cpu_regs.CP0.r[_Rd_] // Fs register
  74. #define _c2dRs_ upse_r3000_cpu_regs.CP2D.r[_Rs_] // Rs cop2 data register
  75. #define _c2dRt_ upse_r3000_cpu_regs.CP2D.r[_Rt_] // Rt cop2 data register
  76. #define _c2dRd_ upse_r3000_cpu_regs.CP2D.r[_Rd_] // Rd cop2 data register
  77. #define _c2dSa_ upse_r3000_cpu_regs.CP2D.r[_Sa_] // Sa cop2 data register
  78. #define _rHi_ upse_r3000_cpu_regs.GPR.n.hi // The HI register
  79. #define _rLo_ upse_r3000_cpu_regs.GPR.n.lo // The LO register
  80. #define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
  81. #define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction
  82. #define _SetLink(x) upse_r3000_cpu_regs.GPR.r[x] = _PC_ + 4; // Sets the return address in the link register
  83. int psxInit();
  84. void psxReset();
  85. void psxShutdown();
  86. void psxException(u32 code, u32 bd);
  87. void psxBranchTest();
  88. void psxExecuteBios();
  89. int upse_r3000_cpu_init(void);
  90. void upse_r3000_cpu_reset(void);
  91. void upse_r3000_cpu_execute(void);
  92. void upse_r3000_cpu_execute_block(void);
  93. void upse_r3000_cpu_clear(u32 Addr, u32 Size);
  94. void upse_r3000_cpu_shutdown(void);
  95. #endif /* __R3000A_H__ */